CWE-1298: Hardware Logic Contains Race Conditions

Base Draft Simple

CWE版本: 4.18

更新日期: 2025-09-09

弱点描述

A race condition in the hardware logic results in undermining security guarantees of the system.

常见后果

影响范围: Access Control

技术影响: Bypass Protection Mechanism Gain Privileges or Assume Identity Alter Execution Logic

潜在缓解措施

阶段: Architecture and Design

描述: Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.

阶段: Implementation

描述: Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.

引入模式

阶段 说明
Architecture and Design -
Implementation -

适用平台

编程语言
Verilog (Undetermined) VHDL (Undetermined)
技术
System on Chip (Undetermined)
关键信息

CWE ID: CWE-1298

抽象级别: Base

结构: Simple

状态: Draft

相关弱点
相关攻击模式
CAPEC-26